Job Description

Position: Senior ASIC Design Engineer VLSI / Digital Design

Location: Austin, TX (Onsite, 5 days/week)

Type: Full-Time, Permanent

Compensation: $160,000 $180,000 base + Meaningful Equity + Full Medical & Dental

Visa: H1-B sponsorship available

About the Company

Our client is a Series D semiconductor innovator revolutionizing programmable coherent DSP (Digital Signal Processing) technology for AI and cloud infrastructure . Their pioneering chip solutions enable faster, more efficient data transmission within and between AI data centres. Backed by leading investors such as Kleiner Perkins, Spark Capital, Mayfield, and Fidelity , this company is shaping the future of AI connectivity with cutting-edge silicon innovation.

About the Role

We are seeking a talented and experienced ASIC/VLSI Design Engineer to join our client's core design team in Austin, TX . You will work on next-generation DSP and communication SoC designs , collaborating with world-class algorithm, verification, and physical design teams to build innovative, high-speed, low-power chips powering tomorrow's AI networks.

Key Responsibilities

• Translate high-level algorithmic requirements into efficient hardware implementations .
• Define micro-architecture , write clean, synthesis-friendly RTL code (Verilog/system Verilog) .
• Collaborate cross-functionally with verification, DFT, and backend teams to ensure design quality.
• Perform synthesis, timing analysis, and optimization for PPA (power, performance, area).
• Participate in design reviews and defend architectural decisions.
• Support IP/SoC integration , interface documentation, and design validation.
• Debug pre- and post-silicon issues using simulation and waveform analysis.
• Contribute to continuous improvement of design methodology and tool usage.

Required Qualifications

• 5+ years of experience as an ASIC/VLSI digital design engineer .
• Proficiency in Verilog/System Verilog RTL coding.
• Solid understanding of ASIC design flow , including synthesis, linting, CDC, and SDC constraints .
• Experience with DFT (scan insertion, ATPG, BIST).
• Strong debugging and analytical skills.
• Bachelor's or master's degree in electrical or computer engineering from a leading university.

Nice to Have

• Exposure to Optical Communication Systems or Ethernet (100G+) .
• Experience with DSP-oriented hardware blocks .
• Familiarity with IP/SoC integration and system-level interfaces.
• Scripting in Python, Perl, or TCL .
• Entrepreneurial, self-driven attitude with ability to work independently and collaboratively.

Why Join

• Be part of a groundbreaking semiconductor startup at the frontier of AI and cloud connectivity .
• Competitive compensation with meaningful equity participation .
• Full medical & dental coverage .
• H1-B sponsorship available.
• Work onsite in Austin, TX , collaborating directly with top-tier silicon architects.

Interview Process

• 3 rounds total (approx. 2 weeks).
• Includes technical and architecture-focused discussions.
• Relocation supports available (case-by-case).

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